MIPS Dependent Features
***********************

GNU AS for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see ``Appendix D: Assembly Language Programming'' in the same work.

Assembler options
=================

The MIPS configurations of GNU AS support these special options:

-G NUM
     Set the ``small data'' limit to N bytes.  The default limit is 8 bytes. See Controlling the use of small data accesses.

-EB
-EL
     Any MIPS configuration of AS can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other).  Use -EB to select big-endian output, and -EL for little-endian.

-KPIC
     Generate SVR4-style PIC.  This option tells the assembler to generate SVR4-style position-independent macro expansions.  It also tells the assembler to mark the output file as PIC.

-mvxworks-pic
     Generate VxWorks PIC.  This option tells the assembler to generate VxWorks-style position-independent macro expansions.

-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6
     Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, -mips3 to the R4000 processor, and -mips4 to the R8000 and R10000 processors. -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively.  You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mgp32
-mfp32
     Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.  -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.

     The .set gp=32 and .set fp=32 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default.

     On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64
-mfp64
     Assume that 64-bit registers are available.  This is provided in the interests of symmetry with -mgp32 and -mfp32.

     The .set gp=64 and .set fp=64 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default.

-mfpxx
     Make no assumptions about whether 32-bit or 64-bit floating-point registers are available. This is provided to support having modules compatible with either -mfp32 or -mfp64. This option can only be used with MIPS II and above.

     The .set fp=xx directive allows a part of an object to be marked as not making assumptions about 32-bit or 64-bit FP registers.  The default value is restored by .set fp=default.

-modd-spreg
-mno-odd-spreg
     Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA.  -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg

-mips16
-no-mips16
     Generate code for the MIPS 16 processor.  This is equivalent to putting .module mips16 at the start of the assembly file.  -no-mips16 turns off this option.

-mmips16e2
-mno-mips16e2
     Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is equivalent to putting .module mips16e2 at the start of the assembly file. -mno-mips16e2 turns off this option.

-mmicromips
-mno-micromips
     Generate code for the microMIPS processor.  This is equivalent to putting .module micromips at the start of the assembly file. -mno-micromips turns off this option.  This is equivalent to putting .module nomicromips at the start of the assembly file.

-msmartmips
-mno-smartmips
     Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications.  This is equivalent to putting .module smartmips at the start of the assembly file. -mno-smartmips turns off this option.

-mips3d
-no-mips3d
     Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.

-mdmx
-no-mdmx
     Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.

-mdsp
-mno-dsp
     Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.

-mdspr2
-mno-dspr2
     Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.

-mdspr3
-mno-dspr3
     Generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option.

-mmt
-mno-mt
     Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option.

-mmcu
-mno-mcu
     Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. -mno-mcu turns off this option.

-mmsa
-mno-msa
     Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns off this option.

-mxpa
-mno-xpa
     Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns off this option.

-mvirt
-mno-virt
     Generate code for the Virtualization Application Specific Extension. This tells the assembler to accept Virtualization instructions. -mno-virt turns off this option.

-minsn32
-mno-insn32
     Only use 32-bit instruction encodings when generating code for the microMIPS processor.  This option inhibits the use of any 16-bit instructions.  This is equivalent to putting .set insn32 at the start of the assembly file.  -mno-insn32 turns off this option.  This is equivalent to putting .set noinsn32 at the start of the assembly file.  By default -mno-insn32 is selected, allowing all instructions to be used.

-mfix7000
-mno-fix7000
     Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

-mfix-rm7000
-mno-fix-rm7000
     Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.

-mfix-loongson2f-jump
-mno-fix-loongson2f-jump
     Eliminate instruction fetch from outside 256M region to work around the Loongson2F jump instructions.  Without it, under extreme cases, the kernel may crash.  The issue has been solved in latest processor batches, but this fix has no side effect to them.

-mfix-loongson2f-nop
-mno-fix-loongson2f-nop
     Replace nops by or at,at,zero to work around the Loongson2F nop errata.  Without it, under extreme cases, the CPU might deadlock.  The issue has been solved in later Loongson2F batches, but this fix has no side effect to them.

-mfix-vr4120
-mno-fix-vr4120
     Insert nops to work around certain VR4120 errata.  This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.

-mfix-vr4130
-mno-fix-vr4130
     Insert nops to work around the VR4130 mflo/mfhi errata.

-mfix-24k
-mno-fix-24k
     Insert nops to work around the 24K eret/deret errata.

-mfix-cn63xxp1
-mno-fix-cn63xxp1
     Replace pref hints 0 - 4 and 6 - 24 with hint 28 to work around certain CN63XXP1 errata.

-m4010
-no-m4010
     Generate code for the LSI R4010 chip.  This tells the assembler to accept the R4010-specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4010 turns off this option.

-m4650
-no-m4650
     Generate code for the MIPS R4650 chip.  This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.

-m3900
-no-m3900
-m4100
-no-m4100
     For each option -mNNNN, generate code for the MIPS RNNNN chip.  This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

-march=CPU
     Generate code for a particular MIPS CPU.  It is exactly equivalent to -mCPU, except that there are more value of CPU understood.  Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, i6400, p6600, loongson2e, loongson2f, loongson3a, octeon, octeon+, octeon2, octeon3, xlr, xlp

     For compatibility reasons, Nx and Bfx are accepted as synonyms for Nf1_1.  These values are deprecated.

-mtune=CPU
     Schedule and tune for a particular MIPS CPU.  Valid CPU values are identical to -march=CPU.

-mabi=ABI
     Record which ABI the source code uses.  The recognized arguments are: 32, n32, o64, 64 and eabi.

-msym32
-mno-sym32
     Equivalent to adding .set sym32 or .set nosym32 to the beginning of the assembler input.  See MIPS Symbol Sizes.

-nocpp
     This option is ignored.  It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing.  With GNU AS, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.

-msoft-float
-mhard-float
     Disable or enable floating-point instructions.  Note that by default floating-point instructions are always allowed even with CPU targets that don't have support for these instructions.

-msingle-float
-mdouble-float
     Disable or enable double-precision floating-point operations.  Note that by default double-precision floating-point operations are always allowed even with CPU targets that don't have support for these operations.

--construct-floats
--no-construct-floats
     The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register.  This feature is useful if the processor support the FR bit in its status  register, and this bit is known (by the programmer) to be set.  This bit prevents the aliasing of the double width register by the single width registers.

     By default --construct-floats is selected, allowing construction of these floating point constants.

--relax-branch
--no-relax-branch
     The --relax-branch option enables the relaxation of out-of-range branches.  Any branches whose target cannot be reached directly are converted to a small instruction sequence including an inverse-condition branch to the physically next instruction, and a jump to the original target is inserted between the two instructions.  In PIC code the jump will involve further instructions for address calculation.

     The BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T, BPOSGE32 and BPOSGE64 instructions are excluded from relaxation, because they have no complementing counterparts.  They could be relaxed with the use of a longer sequence involving another branch, however this has not been implemented and if their target turns out of reach, they produce an error even if branch relaxation is enabled.

     Also no MIPS16 branches are ever relaxed.

     By default --no-relax-branch is selected, causing any out-of-range branches to produce an error.

-mignore-branch-isa
-mno-ignore-branch-isa
     Ignore branch checks for invalid transitions between ISA modes.

     The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label.  If the ISA modes do not match, then such a branch, if taken, will cause the ISA mode to remain unchanged and instructions that follow will be executed in the wrong ISA mode causing the program to misbehave or crash.

     In the case of the BAL instruction it may be possible to relax it to an equivalent JALX instruction so that the ISA mode is switched at the run time as required.  For other branches no relaxation is possible and therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match, and report an error otherwise so that the problem with code can be diagnosed at the assembly time rather than at the run time.

     However some assembly code, including generated code produced by some versions of GCC, may incorrectly include branches to data labels, which appear to require a mode switch but are either dead or immediately followed by valid instructions encoded for the same ISA the branch has been encoded for.  While not strictly correct at the source level such code will execute as intended, so to help with these cases -mignore-branch-isa is supported which disables ISA mode checks for branches.

     By default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error.

-mnan=ENCODING
     This option indicates whether the source code uses the IEEE 2008 NaN encoding (-mnan=2008) or the original MIPS encoding (-mnan=legacy).  It is equivalent to adding a .nan directive to the beginning of the source file.  See MIPS NaN Encodings.

     -mnan=legacy is the default if no -mnan option or .nan directive is used.

--trap
--no-break
     AS automatically macro expands certain division and multiplication instructions to check for overflow and division by zero.  This option causes AS to generate code to take a trap exception rather than a break exception when an error is detected.  The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break
--no-trap
     Generate code to take a break exception rather than a trap exception when an error is detected.  This is the default.

-mpdr
-mno-pdr
     Control generation of .pdr sections.  Off by default on IRIX, on elsewhere.

-mshared
-mno-shared
     When generating code using the Unix calling conventions (selected by -KPIC or -mcall_shared), gas will normally generate code which can go into a shared library.  The -mno-shared option tells gas to generate code which uses the calling convention, but can not go into a shared library.  The resulting code is slightly more efficient.  This option only affects the handling of the .cpload and .cpsetup pseudo-ops.

High-level assembly macros
==========================

MIPS assemblers have traditionally provided a wider range of instructions than the MIPS architecture itself.  These extra instructions are usually referred to as ``macro'' instructions (The term ``macro'' is somewhat overloaded here, since these macros have no relation to those defined by .macro, see .macro.).

Some MIPS macro instructions extend an underlying architectural instruction while others are entirely new.  An example of the former type is and, which allows the third operand to be either a register or an arbitrary immediate value.  Examples of the latter type include bgt, which branches to the third operand when the first operand is greater than the second operand, and ulh, which implements an unaligned 2-byte load.

One of the most common extensions provided by macros is to expand memory offsets to the full address range (32 or 64 bits) and to allow symbolic offsets such as my_data + 4 to be used in place of integer constants.  For example, the architectural instruction lbu allows only a signed 16-bit offset, whereas the macro lbu allows code such as lbu $4,array+32769($5). The implementation of these symbolic offsets depends on several factors, such as whether the assembler is generating SVR4-style PIC (selected by -KPIC, see Assembler options), the size of symbols (see Directives to override the size of symbols), and the small data limit (see Controlling the use of small data accesses).

Sometimes it is undesirable to have one assembly instruction expand to several machine instructions.  The directive .set nomacro tells the assembler to warn when this happens.  .set macro restores the default behavior.

Some macro instructions need a temporary register to store intermediate results.  This register is usually $1, also known as $at, but it can be changed to any core register REG using .set at=REG.  Note that $at always refers to $1 regardless of which register is being used as the temporary register.

Implicit uses of the temporary register in macros could interfere with explicit uses in the assembly code.  The assembler therefore warns whenever it sees an explicit use of the temporary register.  The directive .set noat silences this warning while .set at restores the default behavior.  It is safe to use .set noat while .set nomacro is in effect since single-instruction macros never need a temporary register.

Note that while the GNU assembler provides these macros for compatibility, it does not make any attempt to optimize them with the surrounding code.

Directives to override the size of symbols
==========================================

The n64 ABI allows symbols to have any 64-bit value.  Although this provides a great deal of flexibility, it means that some macros have much longer expansions than their 32-bit counterparts.  For example, the non-PIC expansion of dla $4,sym is usually:

     lui     $4,%highest(sym)
     lui     $1,%hi(sym)
     daddiu  $4,$4,%higher(sym)
     daddiu  $1,$1,%lo(sym)
     dsll32  $4,$4,0
     daddu   $4,$4,$1

whereas the 32-bit expansion is simply:

     lui     $4,%hi(sym)
     daddiu  $4,$4,%lo(sym)

n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion.

You can use the .set sym32 directive to tell the assembler that, from this point on, all expressions of the form SYMBOL or SYMBOL + OFFSET have 32-bit values.  For example:

     .set sym32
     dla     $4,sym
     lw      $4,sym+16
     sw      $4,sym+0x8000($4)

will cause the assembler to treat sym, sym+16 and sym+0x8000 as 32-bit values.  The handling of non-symbolic addresses is not affected.

The directive .set nosym32 ends a .set sym32 block and reverts to the normal behavior.  It is also possible to change the symbol size using the command-line options -msym32 and -mno-sym32.

These options and directives are always accepted, but at present, they have no effect for anything other than n64.

Controlling the use of small data accesses
==========================================

It often takes several instructions to load the address of a symbol. For example, when addr is a 32-bit symbol, the non-PIC expansion of dla $4,addr is usually:

     lui     $4,%hi(addr)
     daddiu  $4,$4,%lo(addr)

The sequence is much longer when addr is a 64-bit symbol. See Directives to override the size of symbols.

In order to cut down on this overhead, most embedded MIPS systems set aside a 64-kilobyte ``small data'' area and guarantee that all data of size N and smaller will be placed in that area. The limit N is passed to both the assembler and the linker using the command-line option -G N, see Assembler options.  Note that the same value of N must be used when linking and when assembling all input files to the link; any inconsistency could cause a relocation overflow error.

The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it.  The size of an external object may be set with the .extern directive.  For example, .extern sym,4 declares that the object at sym is 4 bytes in length, while leaving sym otherwise undefined.

When no -G option is given, the default limit is 8 bytes. The option -G 0 prevents any data from being automatically classified as small.

It is also possible to mark specific objects as small by putting them in the special sections .sdata and .sbss, which are ``small'' counterparts of .data and .bss respectively. The toolchain will treat such data as small regardless of the -G setting.

On startup, systems that support a small data area are expected to initialize register $28, also known as $gp, in such a way that small data can be accessed using a 16-bit offset from that register.  For example, when addr is small data, the dla $4,addr instruction above is equivalent to:

     daddiu  $4,$28,%gp_rel(addr)

Small data is not supported for SVR4-style PIC.

Directives to override the ISA level
====================================

GNU AS supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsN.  N should be a number from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly.  .set mipsN affects not only which instructions are permitted, but also how certain macros are expanded.  .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration.  You can use this feature to permit specific MIPS III instructions while assembling in 32 bit mode.  Use this directive with care!

The .set arch=CPU directive provides even finer control. It changes the effective CPU target and allows the assembler to use instructions specific to a particular CPU.  All CPUs supported by the -march command line option are also selectable by this directive. The original value is restored by .set arch=default.

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor.  Use .set nomips16 to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

The directive .set micromips puts the assembler into microMIPS mode, in which it will assemble instructions for the microMIPS processor.  Use .set nomicromips to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

Directives to control code generation
=====================================

The .module directive allows command line options to be set directly from assembly.  The format of the directive matches the .set directive but only those options which are relevant to a whole module are supported.  The effect of a .module directive is the same as the corresponding command line option.  Where .set directives support returning to a default then the .module directives do not as they define the defaults.

These module-level directives must appear first in assembly.

Traditional MIPS assemblers do not support this directive.

The directive .set insn32 makes the assembler only use 32-bit instruction encodings when generating code for the microMIPS processor. This directive inhibits the use of any 16-bit instructions from that point on in the assembly.  The .set noinsn32 directive allows 16-bit instructions to be accepted.

Traditional MIPS assemblers do not support this directive.

Directives for extending MIPS 16 bit instructions
=================================================

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary.  The directive .set noautoextend will turn this off.  When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000).  The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode.  Traditional MIPS assemblers do not support this directive.

Directive to mark data as an instruction
========================================

The .insn directive tells AS that the following data is actually instructions.  This makes a difference in MIPS 16 and microMIPS modes: when loading the address of a label which precedes instructions, AS automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

The .global and .globl directives supported by AS will by default mark the symbol as pointing to a region of data not code.  This means that, for example, any instructions following such a symbol will not be disassembled by objdump as it will regard them as data.  To change this behavior an optional section name can be placed after the symbol name in the .global directive.  If this section exists and is known to be a code section, then the symbol will be marked as pointing at code not data.  Ie the syntax for the directive is:

.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...,

Here is a short example:

             .global foo .text, bar, baz .data
     foo:
             nop
     bar:
             .word 0x0
     baz:
             .word 0x1

Directives to control the FP ABI
================================

History of FP ABIs
------------------

The MIPS ABIs support a variety of different floating-point extensions where calling-convention and register sizes vary for floating-point data. The extensions exist to support a wide variety of optional architecture features.  The resulting ABI variants are generally incompatible with each other and must be tracked carefully.

Traditionally the use of an explicit .gnu_attribute 4, N directive is used to indicate which ABI is in use by a specific module. It was then left to the user to ensure that command line options and the selected ABI were compatible with some potential for inconsistencies.

Supported FP ABIs
-----------------

The supported floating-point ABI variants are:

0 - No floating-point
     This variant is used to indicate that floating-point is not used within the module at all and therefore has no impact on the ABI.  This is the default.

1 - Double-precision
     This variant indicates that double-precision support is used.  For 64-bit ABIs this means that 64-bit wide floating-point registers are required. For 32-bit ABIs this means that 32-bit wide floating-point registers are required and double-precision operations use pairs of registers.

2 - Single-precision
     This variant indicates that single-precision support is used.  Double precision operations will be supported via soft-float routines.

3 - Soft-float
     This variant indicates that although floating-point support is used all operations are emulated in software.  This means the ABI is modified to pass all floating-point data in general-purpose registers.

4 - Deprecated
     This variant existed as an initial attempt at supporting 64-bit wide floating-point registers for O32 ABI on a MIPS32r2 CPU.  This has been superseded by 5, 6 and 7.

5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
     This variant is used by 32-bit ABIs to indicate that the floating-point code in the module has been designed to operate correctly with either 32-bit wide or 64-bit wide floating-point registers.  Double-precision support is used.  Only O32 currently supports this variant and requires a minimum architecture of MIPS II.

6 - Double-precision 32-bit FPU, 64-bit FPU
     This variant is used by 32-bit ABIs to indicate that the floating-point code in the module requires 64-bit wide floating-point registers. Double-precision support is used.  Only O32 currently supports this variant and requires a minimum architecture of MIPS32r2.

7 - Double-precision compat 32-bit FPU, 64-bit FPU
     This variant is used by 32-bit ABIs to indicate that the floating-point code in the module requires 64-bit wide floating-point registers. Double-precision support is used.  This differs from the previous ABI as it restricts use of odd-numbered single-precision registers.  Only O32 currently supports this variant and requires a minimum architecture of MIPS32r2.

Automatic selection of FP ABI
-----------------------------

In order to simplify and add safety to the process of selecting the correct floating-point ABI, the assembler will automatically infer the correct .gnu_attribute 4, N directive based on command line options and .module overrides.  Where an explicit .gnu_attribute 4, N directive has been seen then a warning will be raised if it does not match an inferred setting.

The floating-point ABI is inferred as follows.  If -msoft-float has been used the module will be marked as soft-float.  If -msingle-float has been used then the module will be marked as single-precision.  The remaining ABIs are then selected based on the FP register width.  Double-precision is selected if the width of GP and FP registers match and the special double-precision variants for 32-bit ABIs are then selected depending on -mfpxx, -mfp64 and -mno-odd-spreg.

Linking different FP ABI variants
---------------------------------

Modules using the default FP ABI (no floating-point) can be linked with any other (singular) FP ABI variant.

Special compatibility support exists for O32 with the four double-precision FP ABI variants.  The -mfpxx FP ABI is specifically designed to be compatible with the standard double-precision ABI and the -mfp64 FP ABIs.  This makes it desirable for O32 modules to be built as -mfpxx to ensure the maximum compatibility with other modules produced for more specific needs.  The only FP ABIs which cannot be linked together are the standard double-precision ABI and the full -mfp64 ABI with -modd-spreg.

Directives to record which NaN encoding is being used
=====================================================

The IEEE 754 floating-point standard defines two types of not-a-number (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs.  The original version of the standard did not specify how these two types should be distinguished.  Most implementations followed the i387 model, in which the first bit of the significand is set for quiet NaNs and clear for signalling NaNs.  However, the original MIPS implementation assigned the opposite meaning to the bit, so that it was set for signalling NaNs and clear for quiet NaNs.

The 2008 revision of the standard formally suggested the i387 choice and as from Sep 2012 the current release of the MIPS architecture therefore optionally supports that form.  Code that uses one NaN encoding would usually be incompatible with code that uses the other NaN encoding, so MIPS ELF objects have a flag (EF_MIPS_NAN2008) to record which encoding is being used.

Assembly files can use the .nan directive to select between the two encodings.  .nan 2008 says that the assembly file uses the IEEE 754-2008 encoding while .nan legacy says that the file uses the original MIPS encoding.  If several .nan directives are given, the final setting is the one that is used.

The command-line options -mnan=legacy and -mnan=2008 can be used instead of .nan legacy and .nan 2008 respectively.  However, any .nan directive overrides the command-line setting.

.nan legacy is the default if no .nan directive or -mnan option is given.

Note that GNU AS does not produce NaNs itself and therefore these directives do not affect code generation.  They simply control the setting of the EF_MIPS_NAN2008 flag.

Traditional MIPS assemblers do not support these directives.

Directives to save and restore options
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The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set.  The .set push directive saves the current settings on a stack.  The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

Directives to control generation of MIPS ASE instructions
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The directive .set mips3d makes the assembler accept instructions from the MIPS-3D Application Specific Extension from that point on in the assembly.  The .set nomips3d directive prevents MIPS-3D instructions from being accepted.

The directive .set smartmips makes the assembler accept instructions from the SmartMIPS Application Specific Extension to the MIPS32 ISA from that point on in the assembly.  The .set nosmartmips directive prevents SmartMIPS instructions from being accepted.

The directive .set mdmx makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the assembly.  The .set nomdmx directive prevents MDMX instructions from being accepted.

The directive .set dsp makes the assembler accept instructions from the DSP Release 1 Application Specific Extension from that point on in the assembly.  The .set nodsp directive prevents DSP Release 1 instructions from being accepted.

The directive .set dspr2 makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point on in the assembly.  This directive implies .set dsp.  The .set nodspr2 directive prevents DSP Release 2 instructions from being accepted.

The directive .set dspr3 makes the assembler accept instructions from the DSP Release 3 Application Specific Extension from that point on in the assembly.  This directive implies .set dsp and .set dspr2.  The .set nodspr3 directive prevents DSP Release 3 instructions from being accepted.

The directive .set mt makes the assembler accept instructions from the MT Application Specific Extension from that point on in the assembly.  The .set nomt directive prevents MT instructions from being accepted.

The directive .set mcu makes the assembler accept instructions from the MCU Application Specific Extension from that point on in the assembly.  The .set nomcu directive prevents MCU instructions from being accepted.

The directive .set msa makes the assembler accept instructions from the MIPS SIMD Architecture Extension from that point on in the assembly.  The .set nomsa directive prevents MSA instructions from being accepted.

The directive .set virt makes the assembler accept instructions from the Virtualization Application Specific Extension from that point on in the assembly.  The .set novirt directive prevents Virtualization instructions from being accepted.

The directive .set xpa makes the assembler accept instructions from the XPA Extension from that point on in the assembly.  The .set noxpa directive prevents XPA instructions from being accepted.

The directive .set mips16e2 makes the assembler accept instructions from the MIPS16e2 Application Specific Extension from that point on in the assembly, whenever in MIPS16 mode.  The .set nomips16e2 directive prevents MIPS16e2 instructions from being accepted, in MIPS16 mode.  Neither directive affects the state of MIPS16 mode being active itself which has separate controls.

Traditional MIPS assemblers do not support these directives.

Directives to override floating-point options
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The directives .set softfloat and .set hardfloat provide finer control of disabling and enabling float-point instructions. These directives always override the default (that hard-float instructions are accepted) or the command-line options (-msoft-float and -mhard-float).

The directives .set singlefloat and .set doublefloat provide finer control of disabling and enabling double-precision float-point operations.  These directives always override the default (that double-precision operations are accepted) or the command-line options (-msingle-float and -mdouble-float).

Traditional MIPS assemblers do not support these directives.

Syntactical considerations for the MIPS assembler
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Special Characters
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The presence of a # on a line indicates the start of a comment that extends to the end of the current line.

If a # appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).

The ; character can be used to separate statements on the same line.